A serial 10 gigabit Ethernet transceiver on digital 0.13/spl mu/m CMOS

Author

Wu, Bin ; Sutu, Yue-Hong ; Ramamurthy, Karthik ; Zheng, Dong ; Cheung, Eugene ; Tran, Toan ; Jiang, Yong ; Rana, Manoj

Author_Institution

BitBlitz Commun. Inc., Milpitas, CA, USA

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

197

Lastpage

200

Abstract

This paper describes a serial 10 gigabit Ethernet transceiver IC. To the extent of our knowledge, this is the first report of such a device on bulk CMOS. It uses a novel analog phase rotator in each of the 5 clock-and-data recovery (CDR) units for an efficient implementation of multi-channel receiver circuits. A substantial amount of digital logic is present on the chip to perform the encoding, decoding, FIFO, MDIO etc. functions as specified by the 802.3ae standard. Sub-picosecond RMS jitter is nevertheless achieved in such a hostile environment. The chip is implemented in a 0.13/spl mu/m digital CMOS process and dissipates 1.5 watts under a 1.5-volt power supply.

Keywords

CMOS digital integrated circuits; IEEE standards; jitter; local area networks; transceivers; 0.13 microns; 1.5 V; 1.5 W; 10 Gbit; IEEE 802.3ae standard; analog phase rotator; bulk CMOS; clock-and-data recovery units; digital CMOS; digital logic; efficient implementation; hostile environment; multichannel receiver circuits; serial Ethernet transceiver; sub-picosecond rms jitter; CMOS integrated circuits; CMOS logic circuits; CMOS process; Clocks; Decoding; Encoding; Ethernet networks; Jitter; Logic devices; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257106

Filename

1257106