Exploring NoC jitter effect on simulation of spiking neural networks

Author

Dytckov, Sergei ; Purohit, Sushri Sunita ; Daneshtalab, Masoud ; Plosila, Juha ; Tenhunen, Hannu

Author_Institution

Dept. of Inf. Technol., Univ. of Turku, Turku, Finland

fYear

2014

fDate

21-25 July 2014

Firstpage

693

Lastpage

696

Abstract

The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational delay to the simulation. The performance degradation is reported.

Keywords

delays; integrated circuit interconnections; jitter; network-on-chip; neural net architecture; NoC jitter effect; communication problem; delay jitter; interconnection network; large-scale neural network simulation; network-on-chip concept; one-to-many neuron connectivity; performance degradation; spiking neural network simulation; spiking neural network simulator; variable communicational delay; Biological neural networks; Computer architecture; Delays; Hardware; Jitter; Neurons; Topology; network-on-chip; self-organizing maps; spiking neural networks;

fLanguage

English

Publisher

ieee

Conference_Titel

High Performance Computing & Simulation (HPCS), 2014 International Conference on

Conference_Location

Bologna

Print_ISBN

978-1-4799-5312-7

Type

conf

DOI

10.1109/HPCSim.2014.6903756

Filename

6903756