Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching

To overcome the problems of traditional delay models, this paper uses a circuit simulator to calculate gate delay in static timing analysis. We analyzed the effect of multiple inputs simultaneous switching(MISS) on gate delay and proposed a MISS model to calculate the worst case gate delay. Based on this model, we developed the test waveform generation algorithms for complementary CMOS logic and pass transistor logic. By combining gate delay simulation with functional model extraction techniques of transistor circuits, we implemented a transistor level static timing analysis tool called SpiceTime. Results on ten IS-CAS85 benchmark circuits indicated that modules of significant size can be verified by SpiceTime with high precisions.