Custom silicon implementation of a delayless acoustic echo canceller algorithm

This paper presents a hardware implementation of a high quality acoustic echo canceller for use in hands-free telecommunication systems. The implementation is based on an algorithm with no delay in the signal path, attractive for communication systems where low delay is crucial. However, a zero delay algorithm has higher complexity compared to other canceller solutions. A custom silicon implementation fulfils quality and realtime operation while sustaining low power consumption. The fabricated processor contains two million transistors, and the core occupies 20 mm/sup 2/ in a 0.35 /spl mu/m CMOS process. At 16 MHz clock frequency, the chip processes 16 bit samples at a rate of 16 kHz, while consuming 55mW for uncorrelated input data.