Cyfield-RISP: An OpenCL-generated processor for reconfigurable hardware

Automated generation of hardware circuits from programming languages is a highly investigated research field. The primary purpose is to reduce the development effort and to speed up the user application. The present work is inspired by the methodology to generate an accelerator for spiking neural networks (SNN). Our approach is to map the loop-parallel kernels of OpenCL to a field programmable gate array (FPGA) to boost up neural computations. The key element is the Cyfield meta-compiler. It generates instruction set processor (RISP) cores that are tailored to provide the minimum functionality for an OpenCL program. This simplifies the automatic generation of processors that perform platform independent C-like sequential program statements in a massive parallel fashion. First synthesis and benchmark results show that the performance of the architecture is scalable.