10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 /spl mu/m CMOS process

Author

Dörrer, Lukas ; Kuttner, Franz ; Wiesbauer, Andreas ; Giandomenico, Antonio Di ; Hartig, Thomas

Author_Institution

Infineon Technol. Austria, Villach, Austria

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

245

Lastpage

248

Abstract

A 10-bit resolution continuous-time multi-bit /spl Sigma//spl Delta/ ADC for UMTS is introduced. A power-efficient implementation of a third-order multi-bit modulator is presented. By using a feedforward architecture and quantizer dynamic element matching the dissipated power can be reduced. Clocked at 104 MHz, the 0.12 /spl mu/m CMOS /spl Sigma//spl Delta/ ADC achieves 60dB peak SNR over a 2 MHz signal bandwidth, consuming 3mW at 1.2V supply.

Keywords

3G mobile communication; CMOS integrated circuits; continuous time systems; feedforward; modulators; quantisation (signal); sigma-delta modulation; 0.12 microns; 1.2 V; 10-bit resolution sigma-delta ADC; 104 MHz; 2 MHz; 3 mW; CMOS process; UMTS; continuous-time sigma-delta ADC; feedforward architecture; multibit sigma-delta ADC; power-efficient implementation; quantizer dynamic element matching; third-order multibit modulator; CMOS process; Clocks; Delay effects; Delta-sigma modulation; Energy consumption; Filters; Jitter; Linearity; Robustness; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257118

Filename

1257118