DocumentCode
2447043
Title
Clock net optimization using active shielding
Author
Kaul, Himanshu ; Sylvester, Dennis ; Blaauw, David
Author_Institution
Dept. of EECS, Michigan Univ., Ann Arbor, MI, USA
fYear
2003
fDate
16-18 Sept. 2003
Firstpage
265
Lastpage
268
Abstract
We propose the use of active shields, which are shield wires that are switched concurrently with the signal wire, to improve performance and reduce inductive ringing for RLC wires. This technique significantly reduces ringing behaviour (up to 4.5/spl times/) and offers better slopes (up to 40% reduction) and signal propagation delays than the traditional (passive) shielding approach, all of which are shown in the context of a clock net optimization.
Keywords
RLC circuits; circuit optimisation; clocks; integrated circuit interconnections; integrated circuit modelling; shielding; RLC wires; active shielding; clock net optimization; inductive ringing reduction; passive shielding approach; ringing behaviour; shield wires; signal propagation delays; signal wire; Capacitance; Clocks; Fingers; Inductance; Integrated circuit interconnections; Monte Carlo methods; Power grids; Propagation delay; Switches; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location
Estoril, Portugal
Print_ISBN
0-7803-7995-0
Type
conf
DOI
10.1109/ESSCIRC.2003.1257123
Filename
1257123
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