DocumentCode :
2447232
Title :
CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures
Author :
Göhringer, Diana ; Hübner, Michael ; Zeutebouo, Etienne Nguepi ; Becker, Jürgen
Author_Institution :
Fraunhofer IOSB, Germany
fYear :
2010
fDate :
19-23 April 2010
Firstpage :
1
Lastpage :
8
Abstract :
Operating systems traditionally handle the task scheduling of one or more application instances on a processor like hardware architecture. Novel runtime adaptive hardware exploits the dynamic reconfiguration on FPGAs, where hardware blocks are generated, started and terminated. This is similar to software tasks in well established operating system approaches. The hardware counterparts to the software tasks have to be transferred to the reconfigurable hardware via a configuration access port. This port enables the allocation of hardware blocks on the FPGA. Current reconfigurable hardware, like e.g. Xilinx Virtex 5 provide two internal configuration access ports (ICAPs), where only one of these ports can be accessed at one point of time. In e.g. a multiprocessor system on an FPGA, it can happen that multiple instances try to access these ports simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled by a special purpose operating system running on an embedded processor. This special purpose operating system, called CAPOS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the service of priority-based access scheduling, hardware task mapping and resource management.
Keywords :
field programmable gate arrays; multiprocessing systems; operating systems (computers); reconfigurable architectures; resource allocation; scheduling; system-on-chip; CAPOS system; Xilinx Virtex 5; configuration access port; field programmable gate arrays; hardware blocks; operating system; priority-based access scheduling; reconfigurable multiprocessor architectures; resource management; runtime scheduling; task mapping; Application software; Computer architecture; Control systems; Field programmable gate arrays; Hardware; Multiprocessing systems; Operating systems; Processor scheduling; Resource management; Runtime; FPGA; MPSoC; Operating System; Reconfigurable Computing; Scheduling; Task Mapping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-6533-0
Type :
conf
DOI :
10.1109/IPDPSW.2010.5470732
Filename :
5470732
Link To Document :
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