New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology

This paper proposes two novel circuit techniques, one each for static and dynamic logic, for ultra-low standby sub-threshold and gate leakage power in future fully-depleted SOI technology. The proposed schemes make intelligent use/combination of SOI dual-V/sub TH/ transistors, supplementary capacitors, forced stacking and V/sub TH-/ wave-pipelining techniques to reduce power in standby mode and maintain/improve active-mode circuit speed. An analytical formula for optimum transistor sizing in the proposed dynamic logic scheme is derived and validated. It is demonstrated that the proposed schemes become very attractive for wide datapath designs in future aggressively scaled SOI technology.