Testing FPGA based reconfigurable system within run time applications

We introduce a technique for testing partially reconfigurable FPGAs. The test technique is intended to be applied in reconfigurable systems in run time applications. Normally, in reconfigurable systems, each FPGA executes many tasks sequentially. Therefore, it is configured many times in run time applications. We propose that each FPGA is tested just before each configuration. The whole system remains functional because other FPGAs are still in function when the target FPGA is under test. Since the FPGA´s transit time from one task to another has a direct consequence on the system delay, the test must be very fast. Therefore, the test proposed targets only a test of tiles where the majority of the data will be configured and only configurable logic blocks actually used are tested. The technique proposed targets test which is achieved within the fault tolerant system, and is very useful in some critical applications with time and resources constraints.