A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks

In this paper, we propose and analyze a high-speed and area-efficient crossbar scheduling algorithm for o-chip interconnection networks. The algorithm is based on a distributed computing over crossbar fabric while conventional algorithms such as round robin are centralized apart from crossbar fabric. Its implementation shows that it can reduce scheduling delay and its area more than 20% and 50%, respectively a compared to a round robin based SLIP algorithm. We apply the algorithm to a HDTV SoC to analyze its feasibility. The proposed algorithm and its implementation are area-efficient and show higher performance for the on-chip interconnection networks.