A 10Gbps/port 8/spl times/8 shared bus switch with embedded DRAM hierarchical output buffer

A hierarchical buffering technique with the embedded DRAM (eDRAM) as a packet buffer is proposed for 10Gbps/port 8/spl times/8 shared bus switch. A prototype chip with 8 input ports and an output port is implemented by 0.16/spl mu/m DRAM technology. To satisfy the required buffering capacity and memory bandwidth of 90Gbps, a 200MHz 32kb SRAM and four 25MHz 1 Mb eDRAM macros are used hierarchically with 512bit interface. The die area is 13.8mm/sup 2/ including SRAM and DRAM.