A simple design methodology for increased ESD robustness of CMOS core cells

Certain ESD failures are caused by the destruction of a single NMOST finger in a core cell. This can be avoided by making the NMOST fingers wide enough to handle the current from the above lying PMOST(s) during an ESD event. The observed failure mechanism is discussed and a model is presented that can predict the critical PMOST width to NMOST finger width ratio for a CMOS core cell. The model has been examined with experiments in a 0.25 /spl mu/m CMOS technology. A straightforward design method is proposed to improve the ESD robustness of core cells for a given CMOS technology and ESD protection library.