High performance 2-D IDCT for Image/Video Decoding based on FPGA

Inverse Discrete Cosine Transform (IDCT) processor for Image/Video Decoding. This design is realized in Xilinx Vertex5 Field Programmable Gate Array (FPGA). The 2-D IDCT decoding processor has advantages of high precision, low complexity and high speed. In this design we uses Loeffler´s fast algorithm to reduce the power consumption. Previously, Zhu proposed a method which was used in IDCT Lee´s algorithm. It uses the favorable combination of the additions and shifts to replace the linear multiplications of butterfly structure in lee´s algorithm. Based on the methodology proposed by Zhu, we improved Loeffler´s algorithm and obtain a high operating frequency and high precision IP. At the same time we can use the parity of the Loeffler´s algorithm to implement this method, which also reduced the complexity of the algorithm. In this paper, we propose an efficient pipelining FPGA implementation of the 2D IDCT. The operating frequency of 2-D IDCT decoder can reach as high as 278 MHz and the precision of coefficient can be at 17 bits.