Performance impact of SMP-cluster on the On-chip Large-scale Parallel Computing architecture

To minimize the delay of the data communication, hierarchical On-chip Large-scale Parallel Computing architectures (OLPCs) with communication locality awareness are recently studied by researchers. This paper proposes a hierarchical architecture consisting of SMP clustered nodes, each of which is structured by more than one baseline cores through centrally-shared memory. The analytical speedup model of the proposed architecture is established by extending Amdahl´ Law. The design space exploitation of the SMP-clustered architecture is investigated through theoretical analysis and experiential values of the parameters used in the speedup model. Finally, some useful suggestions of the future SMP-clustered OLPCs design are presented during the analysis.