Title :
Test strategies for a 40 Gbps framer SoC
Author :
Heineken, Hans T. ; Khare, Jitendra B.
Author_Institution :
Sacremento Design Center, Ample Commun. Inc., Sacremento, CA, USA
Abstract :
This work describes DFT/DFD/DFM strategies implemented on a 40 Gbps framer chip. The device is a 1500 pin, over 10M gate SoC with multiple PLLs/DLLs and 2.5 GHz IOs. Some novel techniques were required to ensure quality and manufacturability. It also describes the various area and design complexity trade-offs that went into the design process.
Keywords :
circuit complexity; delay lock loops; design for manufacture; design for testability; digital phase locked loops; integrated circuit design; integrated circuit testing; system-on-chip; 2.5 GHz; 40 Gbit/s; 40 Gbps framer SoC; DFM; DFT; circuit complexity; design for debug; integrated circuit test method; multiple DLL; multiple PLL; Application specific integrated circuits; Cost function; Design for disassembly; Design for manufacture; Engines; Packaging; SONET; System-on-a-chip; Telecommunications; Testing;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387338
