Title :
Hierarchical DFT methodology - a case study
Author :
Remmers, Jeff ; Villalba, Moe ; Fisette, Richard
Author_Institution :
Plexus Design Solutions Inc., Sudbury, MA, USA
Abstract :
A hierarchical approach to DFT is presented to address the issues encountered when inserting DFT into large SOC designs. There were challenges in implementing this methodology and the real motivation for implementation of a hierarchical DFT is to align with front-end and physical design process. Implementation of this method includes reduced runtime of tools and reduced pattern size. As a result of additional tester memory available using this technique, more testing was implemented. The case study uses a production design with sandburst, Inc (0.13 μ, 4 Mgate chip).
Keywords :
design for testability; integrated circuit design; integrated circuit testing; system-on-chip; DFT methodology; SOC designs; additional tester memory; front end design process; pattern size reduction; physical design process; production design; runtime reduction; sandburst design; Assembly; Clocks; Computer aided software engineering; Concatenated codes; Design methodology; Logic testing; Process design; Production; Tiles; Timing;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387348
