DocumentCode
2448709
Title
A code-less BIST processor for embedded test and in-system configuration of boards and systems
Author
Clark, CJ ; Ricchetti, Mike
Author_Institution
Intellitech Corp., Durham, NH, USA
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
857
Lastpage
866
Abstract
A code-less processor that enables designers to achieve optimal in-system FPGA configuration as well as embed built-in self-test capabilities into boards and systems is presented. This system BIST architecture enables designers to lower system costs and design effort while satisfying test and field engineering requirements for simplified product test. The BIST processor described here provides a structured approach to solve these problems, using infrastructure IP designed for the board and system levels.
Keywords
built-in self test; field programmable gate arrays; logic design; logic testing; microprocessor chips; printed circuit design; printed circuit testing; IP design; built-in self-test; code less BIST processor; embedded test; printed circuit design; printed circuit testing; product test; system BIST architecture; system FPGA configuration; Built-in self-test; Circuit faults; Circuit testing; Costs; Design engineering; EPROM; Field programmable gate arrays; Manufacturing; Software testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1387349
Filename
1387349
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