A VLIW architecture simulator innovative approach for HW-SW co-design

This document describes an innovative approach for simulating a DSP processor with VLIW architecture, the simulator structure and gives a performance comparison with a state of the art simulation tool. The simulation approach is based on a three-dimensional (phase, time, operation) representation of the pipeline in order to “grab”, in a certain time stamp, the complete processor status, taking into account the current status. This approach allows to accurately simulate the C6x behavior, reducing the simulation time compared with other available simulators. Moreover, the VLIW simulator dynamically generating the instruction set is a flexible tool for hardware-software co-design