DocumentCode :
2448861
Title :
Defect coverage analysis of partitioned testing
Author :
Chakravarty, Sreejit ; Savage, Eric W. ; Tran, Eric N.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
907
Lastpage :
915
Abstract :
Research in improving test quality has focused on identifying better fault models and coverage metrics and tools to achieve high coverage. The test generation and test application methodology is usually not considered. We attempt to understand the implication of a test generation and test application methodology, viz, partitioned testing, on product quality. In partitioned testing, patterns are applied to one part of the design while the other parts are maintained in a quiescent state. Quantitative data on several aspects of partitioned testing, using some industrial test cases, are presented. It highlights the need for generating patterns using different partition sizes, generating longer test sequences and the need to include functional testing in the test suite. In addition, we argue that a different metric is needed to evaluate functional pattern quality to cover the gaps identified.
Keywords :
automatic test pattern generation; fault diagnosis; integrated circuit testing; coverage metrics; defect coverage analysis; fault models; functional pattern quality; functional testing; product quality; quiescent state; test pattern generation; test quality improvement; test sequence generation; Built-in self-test; Design methodology; Distributed control; Fault diagnosis; Logic design; Logic testing; Signal design; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1387355
Filename :
1387355
Link To Document :
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