Implementation of a bandwidth-efficient M-FSK demodulator for powerline communications

In this paper, an implementation of a bandwidth-efficient M-ary frequency shift keying (M-FSK) demodulator is performed in a direct mode, by undersampling and analyzing consecutive triplets of signal samples. The method, which will be analyzed, is characterized by low complexity and can be realized in a solid-state circuit or embedded in a programmable device. A DSP based implementation will be presented, consisting of a bandpass filter, an A/D converter and a low cost DSP. The demodulator is targeted to powerline communications and operates at a bit rate of 19.2kbps, achieving a bandwidth usage of 3 bits/Hz and a satisfactory noise performance, optimizing the cost-and -performance to bitrate ratio.