Title :
Programmable at-speed array and functional BIST for embedded DRAM LSI
Author :
Kume, Masaji ; Uehara, Katsutoshi ; Itakura, Minoru ; Sawamoto, Hideo ; Kobayashi, Takehiko ; Hasegawa, Masatoshi ; Hayashi, Hideki
Author_Institution :
Enterprise Server Div., Hitachi Ltd., Kanagawa, Japan
Abstract :
A new approach to DFT (design for test) for an embedded DRAM LSI is proposed in This work. One powerful BIST engine is implemented on the LSI, which executes not only the array BIST for the DRAM and SRAM macros, but also functional BIST for the whole chip. It was implemented in an embedded DRAM cache LSI which is presented together with measured results.
Keywords :
DRAM chips; SRAM chips; built-in self test; cache storage; design for testability; integrated circuit testing; large scale integration; logic testing; programmable logic arrays; BIST engine; DFT; SRAM macros; design for test; embedded DRAM cache LSI; functional BIST; programmable logic arrays; Bandwidth; Built-in self-test; Computer buffers; Costs; Engines; Frequency; Large scale integration; Random access memory; Semiconductor device measurement; System testing;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387364
