MOSFET mismatch in weak/moderate inversion: model needs and implications for analog design

Author

Vancaillie, L. ; Silveira, E. ; Linares-Barranco, B. ; Serrano-Gotarredona, T. ; Flandre, D.

Author_Institution

Microelectron. Lab., Univ. de Louvain, Louvain-la-Neuve, Belgium

fYear

2003

fDate

16-18 Sept. 2003

Firstpage

671

Lastpage

674

Abstract

Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions.

Keywords

MOSFET; analogue integrated circuits; current mirrors; integrated circuit design; integrated circuit modelling; CMOS technologies; MOSFET mismatch; analog design; body effect factor dependence; current mirror case; gate voltage; mismatch measurements; moderate inversion; operating temperature range; weak inversion; CMOS process; CMOS technology; Current measurement; Data mining; MOS devices; MOSFET circuits; Performance evaluation; Semiconductor device modeling; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European

Conference_Location

Estoril, Portugal

Print_ISBN

0-7803-7995-0

Type

conf

DOI

10.1109/ESSCIRC.2003.1257224

Filename

1257224