DocumentCode
2449218
Title
Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models
Author
Irajpour, Shahdad ; Gupta, Sandeep K. ; Breuer, Melvin A.
Author_Institution
Dept. of EE-Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear
2004
fDate
26-28 Oct. 2004
Firstpage
1024
Lastpage
1033
Abstract
All previous approaches for generating tests for crosstalk slow-downs are timing-dependent, i.e., they use the nominal values of gate and wire delays while generating tests. None of these methodologies can be used when a crosstalk slow-down must be considered in the presence of process variations and delay producing defects, since such variations and defects change the delay values from the nominal. We present the first timing-independent approach to generate tests for crosstalk slow-downs. The framework is based upon defining a set of surrogates for each crosstalk slow-down target and generating a test for each surrogate. The timing-independent conditions that a test for each surrogate must satisfy are presented. Under the pin-to-pin delay model, we prove that a set of two-vector sequences that covers every surrogate for a crosstalk slow-down target is guaranteed to detect the target, even in the presence of arbitrary delay variations and delay producing defects. We present a method to identify the crosstalk targets and surrogates for which tests must be generated as well as a test generator that we have implemented. We present extensive experimental results using combinational parts of ISCAS 89 circuits.
Keywords
automatic test pattern generation; combinational circuits; crosstalk; delays; fault diagnosis; ISCAS 89 circuits; combinational circuits; crosstalk slowdown test generation; delay producing defects; gate delays; pin-to-pin delay model; surrogate fault models; timing independent conditions; timing independent crosstalk testing; two vector sequences; wire delays; Circuit faults; Circuit testing; Clocks; Combinational circuits; Crosstalk; Delay effects; Integrated circuit interconnections; Propagation delay; System testing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN
0-7803-8580-2
Type
conf
DOI
10.1109/TEST.2004.1387368
Filename
1387368
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