Title :
Programming customized parallel architectures in FPGA
Author_Institution :
Xilinx, San Jose, CA, USA
Abstract :
Summary form only given. CPUs are multicore (and multi-cache) supported by a coherent, global, shared memory model. FPGAs offer a vast number of distributed programmable function blocks and distributed memory blocks across distributed memory spaces. This presentation will discuss a hybrid computing architecture that unifies the development of applications for a combined CPU-FPGA platform. The proposed programming model is based on message passing (MPI) and distributed memory. NoCs are at the heart of the hybrid platform managing the control and data flows. NoCs are implemented through shared memory buffers on the CPU portion of the hybrid computing platform. On parallel hardware, NoCs are implemented as application-specific point-to-point networks exploiting the abundant routing and switching resources of the FPGA. NoCs enable application-specific memory models while keeping with standard, familiar programming models such as MPI.
Keywords :
field programmable gate arrays; message passing; network-on-chip; parallel architectures; shared memory systems; application-specific memory models; customized parallel architectures; distributed memory blocks; distributed memory spaces; distributed programmable function blocks; field programmable gate array; hybrid CPU-FPGA platform; hybrid computing architecture; message passing; network-on-chip; shared memory buffers; Computer architecture; Field programmable gate arrays; Hardware; Heart; Message passing; Multicore processing; Network-on-a-chip; Parallel architectures; Parallel programming; Routing;
Conference_Titel :
Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-6533-0
DOI :
10.1109/IPDPSW.2010.5470821
