Title :
A 75mW 10bit 120MSample/s parallel pipeline ADC
Author :
Miyazaki, Daisuke ; Furuta, Masanori ; Kawahito, Shoji
Author_Institution :
Res. Inst. of Electron., Shizuoka Univ., Hamamatsu, Japan
Abstract :
This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADC´s. Capacitor mismatch, gain and offset errors are measured by technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3/spl mu/ 2-poly 3-metal CMOS technology. The 10bit 120M sample/s ADC achieves 0.14LSB of DNL and 0.8LSB of INL with very low power dissipation of 75mW at 2V.
Keywords :
CMOS logic circuits; analogue-digital conversion; integrated circuit design; low-power electronics; parallel architectures; pipeline processing; 0.3 micron; 10 bits; 2 V; 75 mW; ADC core; CMOS technology; INL plot; analog-to-digital converter; capacitor mismatch; digital calibration; error correction logic; high-speed ADC; low-power ADC; offset errors; parallel pipeline ADC; pipeline ADC architecture; pseudo-differential ADC; Calibration; Circuits; Clocks; Cost function; Differential amplifiers; Error correction; Pipelines; Sampling methods; Switches; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2003. ESSCIRC '03. Proceedings of the 29th European
Conference_Location :
Estoril, Portugal
Print_ISBN :
0-7803-7995-0
DOI :
10.1109/ESSCIRC.2003.1257236
