A set of traffic models for Network-on-Chip benchmarking

Author

Pekkarinen, Esko ; Lehtonen, Lasse ; Salminen, Erno ; Hämäläinen, Timo D.

Author_Institution

Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland

fYear

2011

fDate

Oct. 31 2011-Nov. 2 2011

Firstpage

78

Lastpage

81

Abstract

This paper presents a set of 9 application traffic models for benchmarking Networks-on-Chip designs. Common benchmarks allow fair comparison, reproduction of research results, and accelerate NoC development. The set is based on real applications found in literature and executable on freely available benchmarking tool called Transaction Generator (TG). It was found that traffic target distribution is far from uniform and bandwidth requirements vary very much between tasks and between applications. TG and the model source codes are freely available. Models are stored in XML format and are based on task graphs with on average 15 processing tasks. The average communication load is about 2 GByte/s.

Keywords

network-on-chip; parallel processing; NoC development; XML format; extensible markup language; network-on-chip benchmarking; network-on-chip design; task graph; traffic model set; traffic target distribution; transaction generator tool; Bandwidth; Benchmark testing; Computational modeling; Generators; Load modeling; Receivers; XML; Multiprocessor System-on-Chip; Network-on-Chip; benchmarking;

fLanguage

English

Publisher

ieee

Conference_Titel

System on Chip (SoC), 2011 International Symposium on

Conference_Location

Tampere

Print_ISBN

978-1-4577-0671-4

Electronic_ISBN

978-1-4577-0670-7

Type

conf

DOI

10.1109/ISSOC.2011.6089221

Filename

6089221