A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. This has resulted in the design of multi-gigahertz microprocessors with unprecedented levels of integration. However, this is posing serious challenges to IC testing and long-term reliability. A major source of failures and test escapes in high performance ICs can be attributed to timing-only parametric failures. We implement a DFT technique to detect delay faults in a full custom 32-bit high performance ALU. We present the energy-delay tradeoffs and scaling trends associated with our DFT technique for the 180 nm-65 nm CMOS technologies. In addition, we demonstrate how this technique can be used to detect delay faults with improved resolution (∼60 ps for 180 nm technology) at relatively low, test mode clock frequencies.