DocumentCode :
2449875
Title :
Risks associated with faults within test pattern compactors and their implications on testing
Author :
Metra, C. ; Mak, TM ; Omana, M.
Author_Institution :
DEIS, Bologna Univ., Italy
fYear :
2004
fDate :
26-28 Oct. 2004
Firstpage :
1223
Lastpage :
1231
Abstract :
We analyze the risks associated with faults affecting a key component block of today´s DFT structures, that is the compactor. We show that, because of compactors´ internal faults, DFT structures may become useless, with consequent dramatic impact on test effectiveness, product quality and defect level. We borrow the well-known fault secure property for DFT compactors and we show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults within compactors. We discuss the fault secureness of some recently proposed compactors and we provide general design rules to be followed to guarantee fault secureness.
Keywords :
design for testability; integrated circuit testing; risk analysis; DFT structures; compactors internal faults; fault secure property; faulty products; product quality; risk analysis; test pattern compactors; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Fabrication; Microelectronics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
Type :
conf
DOI :
10.1109/TEST.2004.1387395
Filename :
1387395
Link To Document :
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