• DocumentCode
    2449918
  • Title

    Low cost concurrent error detection for the advanced encryption standard

  • Author

    Wu, Kaijie ; Ramesh Karri ; Kuznetsov, Grigori ; Goessel, Michael

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Polytech. Univ. Brooklyn, NY, USA
  • fYear
    2004
  • fDate
    26-28 Oct. 2004
  • Firstpage
    1242
  • Lastpage
    1248
  • Abstract
    We present a new low-cost concurrent checking method for the advanced encryption standard (AES) encryption algorithm. In this method, the parity of the 128-bit input is determined and modified step-by-step into the parity of the 128-bit output according to the processing steps of the AES encryption. For the parity-preserving AES steps shift-rows and mix-column no parity modifications are necessary. The modified parity is compared in any round with the actual parity of the outputs of the round. To obtain the hardware costs we implemented this method on a Xilinx Virtex 1000 FPGA. For this implementation, the hardware overhead is about 8% and the additional time delay is about 5%. The method detects technical faults and deliberately injected faults during normal operation.
  • Keywords
    cryptography; delays; error detection; fault diagnosis; field programmable gate arrays; 128 bit; Xilinx Virtex 1000 FPGA; advanced encryption standard; encryption algorithm; error detection; fault detection; low cost concurrent checking method; parity modifications; time delay; Circuit faults; Computer errors; Concurrent computing; Costs; Cryptography; Fault detection; Field programmable gate arrays; Hardware; Smart cards; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2004. Proceedings. ITC 2004. International
  • Print_ISBN
    0-7803-8580-2
  • Type

    conf

  • DOI
    10.1109/TEST.2004.1387397
  • Filename
    1387397