Achieving sub 100 DPPM defect levels on VDSM and nanometer ASICs

Author

Benware, Brady R.

Author_Institution

LSI Logic Corp., Fort Collins, CO, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1418

Abstract

Achieving 100 DPPM on today´s complex ASIC is a realistic but difficult proposition. This work deals in achieving 100 DPPM without functional testing and the advances that are needed to meet these challenges. Structural based test with proper design-for-test (DFT) and scan based testing. The measuring stick for DFT was the stuck-at fault (SAF) test coverage a design could obtain with scan based test. Very deep sub-micron (VDSM) and nanometric designs require additional structural testing such as transition delay fault (TDF) testing. Defect based test methods that focus on outlier identification and removal from test data sets are a critical component in achieving 100 DPPM. Finally, adaptive testing ensure consistent quality and reliability results over the lifetime of the device.

Keywords

application specific integrated circuits; design for testability; fault diagnosis; integrated circuit design; integrated circuit reliability; integrated circuit testing; nanoelectronics; quality control; 100 DPPM defect levels; DFT; adaptive testing; defect based test methods; design for test; device lifetime; integrated circuit reliability; nanometer ASIC; nanometric design; quality control; scan based testing; structural based test; stuck-at fault test; transition delay fault testing; very deep submicron design; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Costs; Design for testability; Fault detection; Large scale integration; Logic testing; System testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387426

Filename

1387426