Sure you can get to 100 DPPM in deep submicron, but it´ll cost ya

Author

Butler, Kenneth M.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2004

fDate

26-28 Oct. 2004

Firstpage

1419

Abstract

The sub-100 DPPM numbers in deep submicron is being built, but the tolls is fairly steep. Traditional methods using simple fault models and pass/fail testing have to be abandoned in favor of probabilistic and statistical approaches. Tests generated for simple fault models detect numerous types of real defects. The cost is increased tester time, though this can be mitigated somewhat by the application of relatively new on-chip pattern compression schemes.

Keywords

automatic test pattern generation; fault diagnosis; integrated circuit testing; statistical analysis; deep submicron technology; defective parts per million; fault models; on-chip pattern compression schemes; probabilistic approach; statistical approach; sub-100 DPPM numbers; test generation; tester; Costs; Fault detection; Geometry; Instruments; Negative bias temperature instability; Niobium compounds; Silicon; System testing; Titanium compounds; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2004. Proceedings. ITC 2004. International

Print_ISBN

0-7803-8580-2

Type

conf

DOI

10.1109/TEST.2004.1387427

Filename

1387427

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2450744