Title :
Test strategies for nanometer technologies
Author :
Sengupta, Sanjay
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The trend toward bigger systems-on-a-chip means that the increase in die size alone add significant DPM, making the goal of double-digit DPM using current methods infeasible. To keep quality under control in nanometer processes, test must target delay defects, noise and process variation. Functional testing of high-performance parts continues to screen significant unique DPM on top of high coverage scan content. The at-speed tests result in heavy yield losses because they are applied in non-native mode, and could target functionally unsensitizable paths. In addition DFT supports reliable at-speed test application methods. With the proliferation of subtle defect types in nanometer processes, targeting defects directly is essential to contain test data volume. To target the defects stochastic process such as N-defect and BIST were used.
Keywords :
built-in self test; design for testability; integrated circuit design; integrated circuit testing; nanoelectronics; quality control; stochastic processes; system-on-chip; BIST; DFT; N-defect process; at-speed test application methods; delay defects; die size; double-digit DPM; functional testing; high coverage scan content; nanometer process; nanometer technology; process variation; quality control; stochastic process; subtle defect types; systems-on-chip; yield losses; Automatic testing; Circuit testing; Costs; Crosstalk; Delay; Feedback; Logic arrays; Manufacturing; Threshold voltage; Wires;
Conference_Titel :
Test Conference, 2004. Proceedings. ITC 2004. International
Print_ISBN :
0-7803-8580-2
DOI :
10.1109/TEST.2004.1387429