• DocumentCode
    2451241
  • Title

    BSLD threshold driven power management policy for HPC centers

  • Author

    Etinski, Maja ; Corbalan, Julita ; Labarta, Jesus ; Valero, Mateo

  • Author_Institution
    Barcelona Supercomput. Center, Barcelona, Spain
  • fYear
    2010
  • fDate
    19-23 April 2010
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    In this paper, we propose a power-aware parallel job scheduler assuming DVFS enabled clusters. A CPU frequency assignment algorithm is integrated into the well established EASY backfilling job scheduling policy. Running a job at lower frequency results in a reduction in power dissipation and accordingly in energy consumption. However, lower frequencies introduce a penalty in performance. Our frequency assignment algorithm has two adjustable parameters in order to enable fine grain energy-performance trade-off control. Furthermore, we have done an analysis of HPC system dimension. This paper investigates whether having more DVFS enabled processors for same load can lead to better energy efficiency and performance. Five workload traces from systems in production use with up to 9 216 processors are simulated to evaluate the proposed algorithm and the dimensioning problem. Our approach decreases CPU energy by 7%- 18% on average depending on allowed job performance penalty. Using the power-aware job scheduling for 20% larger system, CPU energy needed to execute same load can be decreased by almost 30% while having same or better job performance.
  • Keywords
    parallel processing; power aware computing; scheduling; BSLD threshold driven power management; CPU frequency assignment algorithm; DVFS; EASY backfilling job scheduling policy; HPC center; HPC system dimension; dynamic voltage frequency scaling; energy consumption; energy efficiency; power dissipation; power-aware job scheduling; power-aware parallel job scheduler; Algorithm design and analysis; Clustering algorithms; Energy consumption; Energy efficiency; Energy management; Frequency; Performance analysis; Processor scheduling; Production systems; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), 2010 IEEE International Symposium on
  • Conference_Location
    Atlanta, GA
  • Print_ISBN
    978-1-4244-6533-0
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2010.5470913
  • Filename
    5470913