DocumentCode
2451268
Title
Controllable Arbitrary Integer Frequency Divider Based on VHDL
Author
Tian Hongli ; Shi Shuo ; Zhang Jun ; Zhao Hongdong
Author_Institution
Hebei Univ. of Technol., Tianjin, China
fYear
2009
fDate
25-26 April 2009
Firstpage
691
Lastpage
694
Abstract
The key technique for the design of a frequency divider is to find a function between the input and output. In general, the design process and circuit of a frequency divider is complicated, modification and transplantation for it is difficult. A creative design method of CAIFD (Controllable Arbitrary Integer Frequency Divider) is presented in this paper, which uses the VHDL (VHSIC Hardware Description Language ) source code to synthesize a FPGA (Field Programmable Gate Array) or a CPLD (Complex Programmable Logic Device) circuit that produces a 50% duty cycle n (n is a integer and n>0 ) controllable waveform. In order to validate the design method, CAIFD which has different frequency coefficients is simulated in device of ALTERA Corporation´s EP2S15F484C3. Results of the experiment shows that modification and transplantation of CAIFD is easy, moreover the performance is steady and reliable.
Keywords
field programmable gate arrays; frequency dividers; hardware description languages; FPGA; VHDL; complex programmable logic device; controllable arbitrary integer frequency divider; controllable waveform; duty cycle; field programmable gate array; hardware description language; source code; Circuit synthesis; Design methodology; Field programmable gate arrays; Frequency conversion; Frequency synthesizers; Hardware design languages; Process design; Programmable logic arrays; Programmable logic devices; Very high speed integrated circuits; 50% duty cycle; CPLD; FPGA; VHDL; frequency divider;
fLanguage
English
Publisher
ieee
Conference_Titel
Artificial Intelligence, 2009. JCAI '09. International Joint Conference on
Conference_Location
Hainan Island
Print_ISBN
978-0-7695-3615-6
Type
conf
DOI
10.1109/JCAI.2009.62
Filename
5159097
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