Suspended Gate Field Effect Transistor based power management - a 32-bit adder case study

Recent investigations suggest that the Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace traditional high-Vt FETs, utilized as sleep transistors in power management circuits, due to its abrupt switching enabled by electromechanical instability at a certain threshold voltage and its ultra low ldquooffrdquo current (Ioff). This paper presents a preliminary assessment of the SG-FET potential if utilized as sleep transistor in circuits featuring cell based power gating. We first evaluate various SG-FET instances in terms of switching delay, current capability, and leakage. Subsequently, we compare these figures with the once offered by traditional switch transistors utilized in CMOS technologies. Finally, we evaluate the potential implications of the utilization of SG-FETs as sleep transistors in a 90 nm CMOS 32-bit Adder. Our simulations indicate that Ioff is reducing by 10 orders of magnitude, while the active area of the sleep transistor is increasing with 130%.