32-bit RISC CPU Based on MIPS Instruction Fetch Module Design

Author

Yi, Kui ; Ding, Yue-Hua

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., WuHan Polytech. Univ., Wuhan, China

fYear

2009

fDate

25-26 April 2009

Firstpage

754

Lastpage

760

Abstract

In this paper, we analyze MIPS instruction format-, instruction data path-, decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction fetch (ZF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module -, address arithmetic module-, check validity of instruction module-, synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on Quartus ll.

Keywords

instruction sets; microcomputers; reduced instruction set computing; MIPS instruction format; Quartus ll; RISC CPU instruction set; arithmetic module; decoder module function; fetch instruction; instruction data path; instruction fetch module design; latch module; reduced instruction set computing; synchronous control module; Arithmetic; Artificial intelligence; Computer science; Data engineering; Decoding; Design engineering; Information analysis; Pipelines; Reduced instruction set computing; Registers; Data Flow; Data Path; MIPS; Pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Artificial Intelligence, 2009. JCAI '09. International Joint Conference on

Conference_Location

Hainan Island

Print_ISBN

978-0-7695-3615-6

Type

conf

DOI

10.1109/JCAI.2009.158

Filename

5159113