Title :
32 bit Multiplication and Division ALU Design Based on RISC Structure
Author :
Yi, Kui ; Ding, Yue-Hua
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., WuHan Polytech. Univ., Wuhan, China
Abstract :
This paper analyses structure and algorithm of floating-point ALU, and implements multiplication and division operation in the homo-hardware circuit. The floating-point multiplication and division ALU supports floating-point number according with IEEE-754 standard. This ALU adopts 4-level pipelining structure: ´0´ operation number check, exponent addition and subtraction operation, fraction multiplication and division operation, result normalization and round. Each step can act as a single module. Among these modules, there are some registers which can prepare necessary data for next operation.
Keywords :
floating point arithmetic; hardware description languages; logic design; microprocessor chips; pipeline arithmetic; reduced instruction set computing; 32-bit division operation; 32-bit fraction multiplication; 4-level pipelining structure; CPU ALU design; IEEE-754 standard; RISC structure; VHDL; exponent addition; floating-point ALU algorithm; homo-hardware circuit; operation number check; result normalization; subtraction operation; Algorithm design and analysis; Application specific integrated circuits; Arithmetic; Computer science; Design engineering; Digital integrated circuits; Field programmable gate arrays; Pipeline processing; Reduced instruction set computing; System performance; IEEE-754 Standard; VHDL; pipelining;
Conference_Titel :
Artificial Intelligence, 2009. JCAI '09. International Joint Conference on
Conference_Location :
Hainan Island
Print_ISBN :
978-0-7695-3615-6
DOI :
10.1109/JCAI.2009.159
