Analytical placement of mixed-size circuits for better detailed-routability

We propose an analytical placer for generating placement results that can be detailed-routed faster and have fewer violation of design rules. By including a group of pin density constraints in its mathematical formulation, the placer manages to alleviate pin congestion when distributing cells. Moreover, for mixed-size circuits, we adopt a scaled smoothing method to minimize the possible negative influence of fixed macro blocks in placement. As a result, we have few cells overlapping with fixed blocks after global placement, implying that the global placement solution resembles a legal solution more and that legalization has less perturbance to the placement quality. Also, in the final placement result, fewer cells are around macro blocks, whose negative effect in the future routing stage can thus be reduced. Routing solutions obtained by a commercial router show that for most benchmark circuits, detailed routing solutions with fewer violations can be achieved on the placement results generated by our analytical placer.