DocumentCode
2453067
Title
NBTI mitigation by Dynamic Partial Reconfiguration
Author
Carlo, Stefano Di ; Galfano, Salvatore ; Gambardella, Giulio ; Indaco, Marco ; Prinetto, Paolo ; Rolfo, Daniele ; Trotta, Pascal
Author_Institution
Dipt. di Autom. e Inf., Politec. di Torino, Turin, Italy
fYear
2012
fDate
3-5 Oct. 2012
Firstpage
93
Lastpage
96
Abstract
FPGAs achieve smaller geometries and their reliability is becoming a severe issue. Non-functional properties, as Negative Bias Temperature Instability, affect the device functionality. In this work a novel methodology to address this issue is described, exploiting FPGAs flexibility. Dynamic Partial Reconfiguration is used to minimize aging impact on FPGAs´ configuration memory.
Keywords
SRAM chips; field programmable gate arrays; integrated circuit reliability; negative bias temperature instability; FPGA flexibility; FPGA reliability; NBTI mitigation; aging impact minimization; configuration memory; device functionality; dynamic partial reconfiguration; field programmable gate arrays; negative bias temperature instability; nonfunctional properties; Aging; Degradation; Field programmable gate arrays; Logic gates; MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Conference (BEC), 2012 13th Biennial Baltic
Conference_Location
Tallinn
ISSN
1736-3705
Print_ISBN
978-1-4673-2775-6
Type
conf
DOI
10.1109/BEC.2012.6376823
Filename
6376823
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