N-stage pipelined Digital to Analog converter testing

Author

Hamed, S.M. ; Khalil, A.H. ; Abdelhalim, M.B. ; Amer, H.H. ; Madian, A.H.

Author_Institution

Electron. & Commun. Dept., Cairo Univ., Cairo, Egypt

fYear

2012

fDate

3-5 Oct. 2012

Firstpage

109

Lastpage

112

Abstract

Nowadays, mixed analog and digital circuits are of big interest. Digital-to-Analog converters (DACs) are among the main parts of these circuits. Hence, testing the Pipelined DAC (PDAC) is necessary as it is used in many applications. This paper presents a low cost test of a one stage circuit level PDAC. The fault model used in this test consists of catastrophic faults. It is proved that two test inputs are sufficient to detect all faults in this PDAC stage. Based on this result, a general test procedure is developed in order to test an N-stage PDAC. The test procedure was verified using the Eldo simulator provided by Mentor Graphics Corp. on a 90nm MOS model provided by MOSIS.

Keywords

MOS integrated circuits; circuit simulation; digital-analogue conversion; fault tolerant computing; integrated circuit testing; mixed analogue-digital integrated circuits; pipeline processing; DAC; Eldo simulator; MOS model; MOSIS; N-stage pipelined digital-to-analog converter testing; PDAC testing; catastrophic faults; fault detection; fault model; low cost testing; mixed analog-digital circuits; one-stage circuit level PDAC; size 90 nm; Capacitors; Circuit faults; Clocks; Integrated circuit modeling; Operational amplifiers; Switches; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Conference (BEC), 2012 13th Biennial Baltic

Conference_Location

Tallinn

ISSN

1736-3705

Print_ISBN

978-1-4673-2775-6

Type

conf

DOI

10.1109/BEC.2012.6376827

Filename

6376827