DocumentCode
245314
Title
Leveraging the error resilience of machine-learning applications for designing highly energy efficient accelerators
Author
Zidong Du ; Lingamneni, Avinash ; Yunji Chen ; Palem, Krishna ; Temam, Olivier ; Chengyong Wu
Author_Institution
CARCH, ICT, China
fYear
2014
fDate
20-23 Jan. 2014
Firstpage
201
Lastpage
206
Abstract
In recent years, inexact computing has been increasingly regarded as one of the most promising approaches for reducing energy consumption in many applications that can tolerate a degree of inaccuracy. Driven by the principle of trading tolerable amounts of application accuracy in return for significant resource savings - the energy consumed, the (critical path) delay and the (silicon) area being the resources - this approach has been limited to certain application domains. In this paper, we propose to expand the application scope, error tolerance as well as the energy savings of inexact computing systems through neural network architectures. Such neural networks are fast emerging as popular candidate accelerators for future heterogeneous multi-core platforms, and have flexible error tolerance limits owing to their ability to be trained. Our results based on simulated 65nm technology designs demonstrate that the proposed inexact neural network accelerator could achieve 43.91%-62.49% savings in energy consumption (with corresponding delay and area savings being 18.79% and 31.44% respectively) when compared to existing baseline neural network implementation, at the cost of an accuracy loss (quantified as the Mean Square Error (MSE) which increases from 0.14 to 0.20 on average).
Keywords
learning (artificial intelligence); mean square error methods; multiprocessing systems; neural nets; MSE; application accuracy; application scope; critical path delay; energy consumption; energy efficienct accelerators; energy savings; flexible error tolerance limits; future heterogeneous multicore platforms; inexact computing systems; machine-learning applications; mean square error; neural network architectures; resource savings; silicon area; Accuracy; Benchmark testing; Biological neural networks; Hardware; Neurons; Training;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific
Conference_Location
Singapore
Type
conf
DOI
10.1109/ASPDAC.2014.6742890
Filename
6742890
Link To Document