DocumentCode
2453151
Title
Reliability enhancement of event timer calibration by using a dual PLL for the calibrating signal generation
Author
Vedin, V. ; Mezerinsh, A.
Author_Institution
Inst. of Electron. & Comput. Sci., Riga, Latvia
fYear
2012
fDate
3-5 Oct. 2012
Firstpage
113
Lastpage
114
Abstract
An approach to calibration of the DSP-based very high precision event timer is considered. A specific calibration signal is synthesized from the master clock signal by employing a dual PLL circuit. Experimental results obtained by testing a particular event timer confirm high reliability of such solution.
Keywords
calibration; circuit reliability; clocks; digital signal processing chips; phase locked loops; signal generators; signal synthesis; timing circuits; DSP-based very high precision event timer; calibration signal generation; calibration signal synthesis; dual PLL circuit; event timer calibration; event timer testing; master clock signal; phase locked loop; reliability enhancement; Calibration; Clocks; Frequency conversion; Interpolation; Oscillators; Phase locked loops; Temperature measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Conference (BEC), 2012 13th Biennial Baltic
Conference_Location
Tallinn
ISSN
1736-3705
Print_ISBN
978-1-4673-2775-6
Type
conf
DOI
10.1109/BEC.2012.6376828
Filename
6376828
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