Title :
Reliability enhancement of event timer calibration by using a dual PLL for the calibrating signal generation
Author :
Vedin, V. ; Mezerinsh, A.
Author_Institution :
Inst. of Electron. & Comput. Sci., Riga, Latvia
Abstract :
An approach to calibration of the DSP-based very high precision event timer is considered. A specific calibration signal is synthesized from the master clock signal by employing a dual PLL circuit. Experimental results obtained by testing a particular event timer confirm high reliability of such solution.
Keywords :
calibration; circuit reliability; clocks; digital signal processing chips; phase locked loops; signal generators; signal synthesis; timing circuits; DSP-based very high precision event timer; calibration signal generation; calibration signal synthesis; dual PLL circuit; event timer calibration; event timer testing; master clock signal; phase locked loop; reliability enhancement; Calibration; Clocks; Frequency conversion; Interpolation; Oscillators; Phase locked loops; Temperature measurement;
Conference_Titel :
Electronics Conference (BEC), 2012 13th Biennial Baltic
Conference_Location :
Tallinn
Print_ISBN :
978-1-4673-2775-6
DOI :
10.1109/BEC.2012.6376828
