Component priority assignment in the data flow dominated embedded systems with timing constraints

Dataflow dominated embedded systems often use data flow graphs (DFG) as system models. To achieve the desired performance, these systems usually contain a lot of hardware/software components working in parallel. These concurrent and cooperative components result in the contentions for shared resources due to architecture and data dependencies. The approach to solve the contentions can be priority assignments. In this paper we introduce an algorithm which can find out a priority assignment for a given set of components working in parallel with a timing constraint. In addition, the algorithm also provides a fast way to calculate, whether a set of components working in parallel can guarantee a given timing constraint. Hence the algorithm can be applied both in designing phase and implementation phase of hardware/software co-design for embedded systems.