Impact of Cache Coherence Protocols on the Processing of Network Traffic

Since the introduction of the 10 GbE standard in 2002, the ability of general purpose processors to efficiently process network traffic with common protocols such as TCP/IP has been revisited and critically evaluated. However, recent commercially available processors such as Intel^reg Coretrade 2 Duo Processor introduce microarchitectural enhancements that could significantly influence the approach to accelerating network processing. We examine the network performance of a real platform containing Intel^reg Coretrade micro-architecture based processors, the role of coherency and a prototype implementation of direct cache placement (direct cache access or DCA) of inbound network traffic. We observe that a substantial portion of the time relates to the inefficiency of I/O specific coherence protocols in the platform. We demonstrate that a relatively, low complexity implementation of DCA called ´Prefetch Hint´ provides a 15 to 43% speed-up to receive-side processing across a range of I/O sizes and present a detailed characterization of the benefits.