SOI transistor model for fast transient simulation

Progress in semiconductor process technology has made SOI transistors one of the most promising candidates for high performance and low power designs. With smaller diffusion capacitances, SOI transistors switch significantly faster than their traditional bulk MOS counterparts and consume less power per switching. However, design and simulation of SOI MOS circuits is more challenging due to more complex behavior of an SOI transistor involving floating body effects, delay dependence on history of transistor switching, bipolar effect and others. This paper is devoted to developing a fast table model of SOI transistors, suitable for use in fast transistor level simulators. We propose using body charge instead of body potential as an independent variable of the model to improve convergence of circuit simulation integration algorithm. SOI transistor has one additional terminal compared with the bulk MOSFET and hence requires larger tables to model. We propose a novel transformation to reduce number of table dimensions and as a result to make the size of the tables reasonable. The paper also presents efficient implementation of our SOI transistor table model using piece-wise polynomial approximation, nonuniform grid discretization, and splitting the transistor model into the model of its equilibrium and non equilibrium states. The effectiveness of the proposed model is demonstrated by employing it in a fast transistor level simulator to simulate high performance industrial SOI microprocessor circuits.