The development of a 0.25 μm CMOS receiver for GSM

Author

Piazza, Francesco ; Huang, Qiuting

Author_Institution

Integrated Syst. Lab., Eidgenossische Tech. Hochschule, Zurich, Switzerland

fYear

1998

fDate

29 Sep-2 Oct 1998

Firstpage

64

Lastpage

67

Abstract

To meet GSM standards, critical building blocks in the RF front-end must provide low noise figures, high linearity and predictable gain, while requiring as few external passive components and consume as little current as possible. This paper presents a transceiver front-end in 0.25 μm CMOS that includes a 11 mA LNA with 1.9 dB NF, a 6 mA mixer with 12.6 dB NF (SSB), a 71 MHz IF amplifier with programmable gain between -20 and 60 dB in 2 dB steps and an I/Q demodulator with an image rejection of 43.5 dB. The performance of the chip, together with an overall power consumption of 25 mA, makes this chip competitive with most existing BJT solutions

Keywords

CMOS digital integrated circuits; UHF integrated circuits; cellular radio; digital radio; digital signal processing chips; radio receivers; 0 to 60 dB; 0.25 μm CMOS receiver; 0.25 micron; 11 mA; 25 mA; 6 mA; 71 MHz; GSM; I/Q demodulator; IF amplifier; LNA; RF front-end; development; image rejection; mixer; performance; power consumption; programmable gain; transceiver front-end; Costs; Filters; GSM; Impedance matching; Inductors; Linearity; Noise measurement; Parasitic capacitance; Production; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems, and Electronics, 1998. ISSSE 98. 1998 URSI International Symposium on

Conference_Location

Pisa

Print_ISBN

0-7803-4900-8

Type

conf

DOI

10.1109/ISSSE.1998.738039

Filename

738039