A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules

Adaptive logic module (ALM) in modern field programmable gate array can serve as one 6-input lookup table (LUT) or two smaller lookup tables under certain constraints. In a typical design flow, a netlist of LUTs formed after technology mapping has to be merged into ALMs and then packed into coarse-grained logic blocks (CLBs) before placement and routing. How the LUTs are merged and the ALMs are packed has a significant impact on the quality of the placement. We propose a novel wirelength-driven algorithm to merge the LUTs and pack the ALMs to ensure that it will not adversely affect the final wire-length. Experimental results show that substituting AAPack [8] by our algorithm yields about 14.54% reduction in number of tracks required for routing and 17.97% wirelength improvement for ALM-based FPGA. Applying our algorithm to traditional FPGA, the minimum channel width and wirelength are reduced by 16.59% and 17.57%, respectively, compared to T-VPack.