DocumentCode
2454695
Title
Impact of lithography variations on advanced CMOS devices
Author
Lorenz, J. ; Kampen, C. ; Burenkov, A. ; Fühner, T.
Author_Institution
Fraunhofer Inst. fur Integrierte Syst. und Bauelementetechnologie IISB, Erlangen, Germany
fYear
2009
fDate
27-29 April 2009
Firstpage
17
Lastpage
18
Abstract
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.
Keywords
CMOS integrated circuits; MOSFET; lithography; technology CAD (electronics); CMOS device; TCAD simulation software; electrical properties; lithography process; size 32 nm; CMOS process; Circuit simulation; Circuits and systems; Doping; Inverters; Investments; Lithography; MOSFETs; Manufacturing processes; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on
Conference_Location
Hsinchu
ISSN
1524-766X
Print_ISBN
978-1-4244-2784-0
Electronic_ISBN
1524-766X
Type
conf
DOI
10.1109/VTSA.2009.5159272
Filename
5159272
Link To Document