DocumentCode :
2454787
Title :
A new ATPG algorithm to limit test set size and achieve multiple detections of all faults
Author :
Lee, Sooryong ; Cobb, Brad ; Dworak, Jennifer ; Grimaila, Michael R. ; Mercer, M. Ray
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear :
2002
fDate :
2002
Firstpage :
94
Lastpage :
99
Abstract :
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of each fault site lead to increased test set size and require more tester memory. In this paper we propose a new ATPG algorithm to find a near-minimal test pattern set that detects faults multiple times and achieves excellent defective part level. This greedy approach uses 3-value fault simulation to estimate the potential value of each vector candidate at each stage of ATPG. The result shows generation of a close to minimal vector set is possible only using dynamic compaction techniques in most cases. Finally, a systematic method to trade-off between defective part level and test size is also presented
Keywords :
automatic test pattern generation; fault simulation; ATPG algorithm; defective part level; dynamic compaction; fault simulation; multiple fault detection; test set size; Automatic test pattern generation; Circuit faults; Circuit testing; Compaction; Electrical fault detection; Fault detection; Manufacturing; Predictive models; System testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings
Conference_Location :
Paris
ISSN :
1530-1591
Print_ISBN :
0-7695-1471-5
Type :
conf
DOI :
10.1109/DATE.2002.998255
Filename :
998255
Link To Document :
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